This research addresses the challenges faced by space applications due to high-energy ionizing particles in the space environment, particularly when using commercial Off-The-Shelf (COTS) components like Field Programmable Gate Arrays (FPGAs) and soft-core processors like RISC-V. Our study introduces a methodology for evaluating the reliability of a state-of-the-art RISC-V processor intended for space missions, establishing a connection between space conditions, Single Event Upset (SEU) fault estimation, and emulation. Focusing on the space environment around a telecommunication satellite, we analyze particle fluxes and their impact on SRAM-based FPGAs using proton radiation test data. By integrating this data, we estimate the SEU rate per mission day caused by the specific radiation environment. Subsequently, we assess the suitability of the NEORV32 processor for operation in such an environment by implementing it in the target FPGA and conducting SEU emulation through fault injection campaigns. Our primary goal is to determine the design mean time to failure within the space environment where the processor is expected to function, a critical metric for implementing effective mitigation strategies for space mission designs. The obtained results, covering worst-case scenarios, suggest that RISC-V-based architectures prove resilient and adaptable for successful deployment in space missions.

Assessment of RISC-V Processor Suitability for Satellite Applications / Vacca, Eleonora; Cora, Giorgio; Azimi, Sarah; Sterpone, Luca. - (In corso di stampa). (Intervento presentato al convegno 21st ACM International Conference on Computing Frontiers tenutosi a Ischia (ITA) nel May 7-9, 2024).

Assessment of RISC-V Processor Suitability for Satellite Applications

Eleonora Vacca;Giorgio Cora;Sarah Azimi;Luca Sterpone
In corso di stampa

Abstract

This research addresses the challenges faced by space applications due to high-energy ionizing particles in the space environment, particularly when using commercial Off-The-Shelf (COTS) components like Field Programmable Gate Arrays (FPGAs) and soft-core processors like RISC-V. Our study introduces a methodology for evaluating the reliability of a state-of-the-art RISC-V processor intended for space missions, establishing a connection between space conditions, Single Event Upset (SEU) fault estimation, and emulation. Focusing on the space environment around a telecommunication satellite, we analyze particle fluxes and their impact on SRAM-based FPGAs using proton radiation test data. By integrating this data, we estimate the SEU rate per mission day caused by the specific radiation environment. Subsequently, we assess the suitability of the NEORV32 processor for operation in such an environment by implementing it in the target FPGA and conducting SEU emulation through fault injection campaigns. Our primary goal is to determine the design mean time to failure within the space environment where the processor is expected to function, a critical metric for implementing effective mitigation strategies for space mission designs. The obtained results, covering worst-case scenarios, suggest that RISC-V-based architectures prove resilient and adaptable for successful deployment in space missions.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2988775