RISC-V soft processors are attractive for various applications, including mission-critical ones, thanks to their reduced costs and high flexibility. Despite their growing popularity, reliability analysis of such platforms is still in an early stage, mainly relying on system-level analysis only, leaving module-level assessment unexplored. Such limitations hinder the development of mitigation strategies that could effectively focus on vulnerabilities within a RISC-V soft processor system. We propose a methodology for evaluating the module-wise reliability of a RISC-V soft processor based on fine-grained fault injection, custom layout placement, and fault analysis. Through this approach, we can provide insights into the critical elements of the processor, identifying the most susceptible to faults, both at the module and system levels. The presented results enhance comprehension of weak points within the processor, paving the way for creating robust and dependable RISC-V systems.
A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical Systems / Cora, Giorgio; De Sio, Corrado; Rizzieri, Daniele; Azimi, Sarah; Sterpone, Luca. - ELETTRONICO. - (2024), pp. 31-36. (Intervento presentato al convegno 27th International Symposium on Design and Diagnostics of Electronic Circuits and Systems tenutosi a Kielce (POL) nel 03-05 April 2024) [10.1109/DDECS60919.2024.10508921].
A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical Systems
Cora, Giorgio;De Sio, Corrado;Rizzieri, Daniele;Azimi, Sarah;Sterpone, Luca
2024
Abstract
RISC-V soft processors are attractive for various applications, including mission-critical ones, thanks to their reduced costs and high flexibility. Despite their growing popularity, reliability analysis of such platforms is still in an early stage, mainly relying on system-level analysis only, leaving module-level assessment unexplored. Such limitations hinder the development of mitigation strategies that could effectively focus on vulnerabilities within a RISC-V soft processor system. We propose a methodology for evaluating the module-wise reliability of a RISC-V soft processor based on fine-grained fault injection, custom layout placement, and fault analysis. Through this approach, we can provide insights into the critical elements of the processor, identifying the most susceptible to faults, both at the module and system levels. The presented results enhance comprehension of weak points within the processor, paving the way for creating robust and dependable RISC-V systems.File | Dimensione | Formato | |
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https://hdl.handle.net/11583/2987728