A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip

The number and complexity of the Automotive Systems-on-Chip have grown dramatically and continuously in the last decades to satisfy the demand for new features in next-generation vehicles. On balance, very extensive test sets are needed to ensure products quality. All these tests are expensive in terms of equipment, and chip-makers are struggling to reduce devices that undergo the entire test process. The ability to isolate failing devices as soon as possible in the production line is crucial to saving money. Despite ATPG efforts being the first solution to reach high levels of coverage, they lead to a considerable amount of memory requirements and unacceptable test times. This paper focuses on test cost reduction based on the analysis of the circuit topology. The assumption done in this work is that the circuit nodes located in the densest areas are likely to be those that will show more defective behaviors. Therefore, we propose to focus the ATPG efforts on addressing first a subset of faults selected from the densest areas of the device. Such ATPG patterns will be less than the complete set but preserve the coverage of the parts that will show more faults. When applied at the wafer sort level, this technique reduces test time and tester memory demands while still screening out the vast majority of defective devices. Afterwards, the Test escapes at the package tests are minimized, and the defective behaviors are limited to the less critical portions of the circuit, which are less likely to fail. The experimental results are reported for a complex Automotive System-on-Chip belonging to the SPC58 family of STMicroelectronics with around 700K Flip Flops and 20 million gates, and they demonstrate the approach feasibility.