To ensure the highest quality products to be shipped to market and to guarantee they will keep working for their lifecycle expectation is a primary goal for automotive chip-makers. Indeed, strong efforts are needed to refine and to strengthen manufacturing test procedures such that very few latent faults are left in the overall population of chips. Nevertheless, an high quality production must be followed by in-field reliability; the development of strategies and activities devised to face front lifetime critical issues has also a very high priority. This paper encompasses several contributions including the description and results obtained by (1) a very accurate method to evaluate the power consumption along FLASH memory manufacturing test, (2) an effective generation strategy for Software-Based Self-Test of multi-core, AI oriented computer architectures and (3) a high-level and very fast architectural emulator for Systems-on-Chip to be used for prototyping irradiation experiments and to forecast campaigns results with a good grade of accuracy about single-event-upsets on processors and peripheral cores.

Industrial best practice: cases of study by automotive chip- makers / Abbati, L. Degli; Ullmann, R.; Paganini, G.; Coppetta, M.; Zaia, L.; Huard, V.; Montfort, O.; Cantoro, R.; Insinga, G.; Venini, F.; Calao, P.; Bernardi, P.. - (2021), pp. 1-6. ((Intervento presentato al convegno 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) nel 06-08 October 2021 [10.1109/DFT52944.2021.9568350].

Industrial best practice: cases of study by automotive chip- makers

Paganini, G.;Cantoro, R.;Insinga, G.;Venini, F.;Calao, P.;Bernardi, P.
2021

Abstract

To ensure the highest quality products to be shipped to market and to guarantee they will keep working for their lifecycle expectation is a primary goal for automotive chip-makers. Indeed, strong efforts are needed to refine and to strengthen manufacturing test procedures such that very few latent faults are left in the overall population of chips. Nevertheless, an high quality production must be followed by in-field reliability; the development of strategies and activities devised to face front lifetime critical issues has also a very high priority. This paper encompasses several contributions including the description and results obtained by (1) a very accurate method to evaluate the power consumption along FLASH memory manufacturing test, (2) an effective generation strategy for Software-Based Self-Test of multi-core, AI oriented computer architectures and (3) a high-level and very fast architectural emulator for Systems-on-Chip to be used for prototyping irradiation experiments and to forecast campaigns results with a good grade of accuracy about single-event-upsets on processors and peripheral cores.
978-1-6654-1609-2
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2939953