In this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE.
A macro-model for the efficient simulation of an ADC-based RNG / Pareschi, F.; Setti, G.; Rovatti, R.. - STAMPA. - (2005), pp. 4349-4352. ((Intervento presentato al convegno IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 tenutosi a Kobe, jpn nel May 23-26, 2005.
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Titolo: | A macro-model for the efficient simulation of an ADC-based RNG |
Autori: | |
Data di pubblicazione: | 2005 |
Abstract: | In this paper we present a macro-model for a true random number generator which internally exploi...ts a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE. |
ISBN: | 0-7803-8834-8 |
Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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C1L-N3.pdf | Editorial Version | 2a Post-print versione editoriale / Version of Record | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
ISCAS2005-macromodel.pdf | Author version of the Paper | 2. Post-print / Author's Accepted Manuscript | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri |
http://hdl.handle.net/11583/2850181