In this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE.

A macro-model for the efficient simulation of an ADC-based RNG / Pareschi, F.; Setti, G.; Rovatti, R.. - STAMPA. - (2005), pp. 4349-4352. ((Intervento presentato al convegno IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 tenutosi a Kobe, jpn nel May 23-26, 2005 [10.1109/ISCAS.2005.1465594].

A macro-model for the efficient simulation of an ADC-based RNG

Pareschi F.;Setti G.;
2005

Abstract

In this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2850181