Archivio Istituzionale della RicercaWe propose a workflow for the analysis and mitigation of 3D ICs to Single Event Transient by upsizing the sensitive transistors. The workflow is applied to 45-nm 3D LUT and the results show a 37% reduction in failure rate.
On the Mitigation of Single Event Transient in 3D LUT by In-Cell Layout Resizing / Azimi, Sarah; Du, Boyang; DE SIO, Corrado; Sterpone, Luca. - ELETTRONICO. - (2020), pp. 1-4. (Intervento presentato al convegno European Conference on Radiation and its Effects on Components and Systems (RADECS) tenutosi a Online event) [10.1109/RADECS50773.2020.9857719].
On the Mitigation of Single Event Transient in 3D LUT by In-Cell Layout Resizing
Sarah Azimi;Boyang Du;Corrado De Sio;Luca Sterpone
2020
Abstract
We propose a workflow for the analysis and mitigation of 3D ICs to Single Event Transient by upsizing the sensitive transistors. The workflow is applied to 45-nm 3D LUT and the results show a 37% reduction in failure rate.
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Utilizza questo identificativo per citare o creare un link a questo documento:
https://hdl.handle.net/11583/2844994