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Testing logic cores using a BIST P1500 compliant approach: a case of study
2005 Bernardi, Paolo; Masera, Guido; Quaglio, Federico; SONZA REORDA, Matteo
Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach
2019 SONZA REORDA, Matteo; Rodriguez Condia Josie, E.
Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy
2020 Rodriguez Condia, Josie Esteban; Sonza Reorda, M.
The Product Machine and Implicit Enumeration to prove FSMs correct
1991 Camurati, Paolo Enrico; Gilli, Marco; Prinetto, Paolo Ernesto; SONZA REORDA, Matteo
The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy
1998 Corno, Fulvio; SONZA REORDA, Matteo; Squillero, Giovanni
The training environment for the course on microprocessor systems at the Politecnico di Torino
1998 Rebaudengo, Maurizio; SONZA REORDA, Matteo
The use of model checking in ATPG for sequential circuits
1991 Camurati, Paolo Enrico; Gilli, Marco; Prinetto, Paolo Ernesto; SONZA REORDA, Matteo
Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard
2018 Sini, Jacopo; Sonza Reorda, Matteo; Violante, Massimo; Sarson, Peter
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects
2017 Flenker, Tino; Malburg, Jan; Fey, Goerschwin; Avramenko, Serhiy; Violante, Massimo; SONZA REORDA, Matteo
Transformation-based peak power reduction for test sequences
1999 Corno, Fulvio; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Violante, Massimo
Citazione | Data di pubblicazione | Autori | File |
---|---|---|---|
Testing logic cores using a BIST P1500 compliant approach: a case of study / Bernardi, Paolo; Masera, Guido; Quaglio, Federico; SONZA REORDA, Matteo. - 3:(2005), pp. 228-233. (Intervento presentato al convegno Design, Automation and Test in Europe Conference and Exhibition (DATE2005) tenutosi a Munich nel 7-11 Marzo 2005) [10.1109/DATE.2005.305]. | 1-gen-2005 | BERNARDI, PAOLOMASERA, GuidoQUAGLIO, FEDERICOSONZA REORDA, Matteo | - |
Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach / SONZA REORDA, Matteo; Rodriguez Condia Josie, E.. - STAMPA. - (2019). (Intervento presentato al convegno 2019 IEEE 25th International Symposium on On-Line Testing And Robust System Design (IOLTS) tenutosi a Rhodes (Greece) nel 1-3 July 2019) [10.1109/IOLTS.2019.8854463]. | 1-gen-2019 | Sonza Reorda MatteoRodriguez Condia Josie E. | Camera_Ready_final.pdf; 08854463.pdf |
Testing the Divergence Stack Memory on GPGPUs: A Modular in-Field Test Strategy / Rodriguez Condia, Josie Esteban; Sonza Reorda, M.. - ELETTRONICO. - (2020), pp. 153-158. (Intervento presentato al convegno 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020 tenutosi a usa nel 5-7 Oct. 2020) [10.1109/VLSI-SOC46417.2020.9344088]. | 1-gen-2020 | Rodriguez Condia, Josie EstebanSonza Reorda, M. | paper open source.pdf; 09344088.pdf |
The Product Machine and Implicit Enumeration to prove FSMs correct / Camurati, Paolo Enrico; Gilli, Marco; Prinetto, Paolo Ernesto; SONZA REORDA, Matteo. - (1991), pp. 51-62. (Intervento presentato al convegno CHARME 1991: Advanced Research Workshop on Correct Hardware Design Methodologies tenutosi a Torino (Italy) nel June 1991). | 1-gen-1991 | CAMURATI, Paolo EnricoGILLI, MARCOPRINETTO, Paolo ErnestoSONZA REORDA, Matteo | - |
The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy / Corno, Fulvio; SONZA REORDA, Matteo; Squillero, Giovanni. - (1998), pp. 349-355. (Intervento presentato al convegno SAC) [10.1145/330560.330838]. | 1-gen-1998 | CORNO, FulvioSONZA REORDA, MatteoSQUILLERO, Giovanni | - |
The training environment for the course on microprocessor systems at the Politecnico di Torino / Rebaudengo, Maurizio; SONZA REORDA, Matteo. - (1998). (Intervento presentato al convegno WCAE '98 Proceedings of the 1998 workshop on Computer architecture education) [10.1145/1275182.1275190]. | 1-gen-1998 | REBAUDENGO, MaurizioSONZA REORDA, Matteo | - |
The use of model checking in ATPG for sequential circuits / Camurati, Paolo Enrico; Gilli, Marco; Prinetto, Paolo Ernesto; SONZA REORDA, Matteo. - 531:(1991), pp. 86-95. (Intervento presentato al convegno Computer-Aided Verification 2nd International Conference, CAV '90 tenutosi a New Brunswick, NJ (USA) nel June 18-21, 1990) [10.1007/BFb0023722]. | 1-gen-1991 | CAMURATI, Paolo EnricoGILLI, MARCOPRINETTO, Paolo ErnestoSONZA REORDA, Matteo | - |
Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard / Sini, Jacopo; Sonza Reorda, Matteo; Violante, Massimo; Sarson, Peter. - ELETTRONICO. - (2018). (Intervento presentato al convegno 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS) tenutosi a Platja d’Aro, Costa Brava (ESP) nel July 2-4, 2018) [10.1109/IOLTS.2018.8474083]. | 1-gen-2018 | Sini, JacopoSonza Reorda, MatteoViolante, Massimo + | camera_ready.pdf; Towards_an_automatic_approach_for_hardware_verification_according_to_ISO_26262_functional_safety_standard.pdf |
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects / Flenker, Tino; Malburg, Jan; Fey, Goerschwin; Avramenko, Serhiy; Violante, Massimo; SONZA REORDA, Matteo. - 2017-:(2017), pp. 533-538. (Intervento presentato al convegno 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 tenutosi a deu nel 2017) [10.1109/ISVLSI.2017.99]. | 1-gen-2017 | AVRAMENKO, SERHIYVIOLANTE, MASSIMOSONZA REORDA, MATTEO + | - |
Transformation-based peak power reduction for test sequences / Corno, Fulvio; Rebaudengo, Maurizio; SONZA REORDA, Matteo; Violante, Massimo. - (1999), pp. 78-83. (Intervento presentato al convegno Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on tenutosi a Como, I nel 4-5 Mar 1999) [10.1109/LPD.1999.750406]. | 1-gen-1999 | CORNO, FulvioREBAUDENGO, MaurizioSONZA REORDA, MatteoVIOLANTE, MASSIMO | - |
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Data di pubblicazione
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- 2020 - 2023 70
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Editore
- IEEE 131
- IEEE Computer Society 44
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Keyword
- Reliability 12
- SBST 12
- Safety 10
- Electrical and Electronic Enginee... 9
- Graphics Processing Units (GPUs) 9
- Hardware and Architecture 8
- Reliability and Quality 7
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- software-based self-test 7
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