Abstract—Nanometric circuits and systems are increasingly susceptible to delay defects. This paper describes a strategy for the diagnosis of transition- delay faults in full-scan systems-on-a-chip (SOCs). The proposed methodology takes advantage of a suitably generated software-based self-test test set and of the scan-chains included in the final SOC design. Effectiveness and feasibility of the proposed approach were evaluated on a nanometric SOC test vehicle including an 8-bit microcontroller, some memory blocks and an arithmetic core, manufactured by STMicroelectronics. Results show that the proposed technique can achieve high diagnostic resolution while maintaining a reasonable application time.
Effective Diagnostic Pattern Generation Strategy forTransition-Delay Faults in Full-Scan SOCs / APPELLO D; BERNARDI P; GROSSO M.; SANCHEZ E; SONZA REORDA M. - In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. - ISSN 1063-8210. - 17 (11)(2009), pp. 1654-1659.
|Titolo:||Effective Diagnostic Pattern Generation Strategy forTransition-Delay Faults in Full-Scan SOCs|
|Data di pubblicazione:||2009|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1109/TVLSI.2008.2006177|
|Appare nelle tipologie:||1.1 Articolo in rivista|