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Accelerating and pruning CNNs for semantic segmentation on FPGA
2022 Mori, Pierpaolo; Vemparala, Manoj-Rohit; Fasfous, Nael; Mitra, Saptarshi; Sarkar, Sreetama; Frickenstein, Alexander; Frickenstein, Lukas; Helms, Domenik; Nagaraja, Naveen-Shankar; Stechele, Walter; Passerone, Claudio
HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures
2022 Valpreda, Emanuele; Mori, Pierpaolo; Fasfous, Nael; Vemparala, Manoj Rohit; Frickenstein, Alexander; Frickenstein, Lukas; Stechele, Walter; Passerone, Claudio; Masera, Guido; Martina, Maurizio
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Accelerating and pruning CNNs for semantic segmentation on FPGA / Mori, Pierpaolo; Vemparala, Manoj-Rohit; Fasfous, Nael; Mitra, Saptarshi; Sarkar, Sreetama; Frickenstein, Alexander; Frickenstein, Lukas; Helms, Domenik; Nagaraja, Naveen-Shankar; Stechele, Walter; Passerone, Claudio. - STAMPA. - DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference:(2022), pp. 145-150. ((Intervento presentato al convegno Proceedings of the 59th ACM/IEEE Design Automation Conference tenutosi a San Francisco (USA) nel 10-14 luglio 2022 [10.1145/3489517.3530424]. | 1-gen-2022 | Mori, PierpaoloPasserone,Claudio + | 3489517.3530424.pdf |
| HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures / Valpreda, Emanuele; Mori, Pierpaolo; Fasfous, Nael; Vemparala, Manoj Rohit; Frickenstein, Alexander; Frickenstein, Lukas; Stechele, Walter; Passerone, Claudio; Masera, Guido; Martina, Maurizio. - In: ELECTRONICS. - ISSN 2079-9292. - ELETTRONICO. - 11:18(2022), p. 2933. [10.3390/electronics11182933] | 1-gen-2022 | Valpreda, EmanueleMori, PierpaoloPasserone, ClaudioMasera, GuidoMartina, Maurizio + | electronics-11-02933-1.pdf; HW_Flow_Fusion__Inter_Layer_Scheduling_for_Convolutional_Neural_Network_Accelerators_with_Dataflow_Architectures.pdf |