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Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse
2019 Mocerino, Luca; Tenace, V.; Calimera, A.
A compression-driven training framework for embedded deep neural networks
2018 Grimaldi, M.; Pugliese, Federico; Tenace, V.; Calimera, A.
Inferential Logic: A Machine Learning Inspired Paradigm for Combinational Circuits
2018 Tenace, V.; Calimera, A.
Multiplication by Inference using Classification Trees: A Case-Study Analysis
2018 Rizzo, Roberto Giorgio; Tenace, Valerio; Calimera, Andrea
Activation-kernel extraction through machine learning
2017 Tenace, Valerio; Calimera, Andrea
Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies
2016 Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture
2016 Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits
2016 Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization
2015 Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Amaru', LUCA GAETANO; De Micheli, Giovanni; Gaillardon, Pierre Emmanuel
One-pass logic synthesis for graphene-based Pass-XNOR logic circuits
2015 Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits
2014 Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits
2014 Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation
2012 Tenace, Valerio; Miryala, Sandeep; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo
NBTI effects on tree-like clock distribution networks
2012 Wei, L.; Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse / Mocerino, L., Tenace, V., Calimera, A.. - (2019), pp. 848-853. (22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019 Firenze Fiera, ita 2019) [10.23919/DATE.2019.8714880]. | 1-gen-2019 | MOCERINO, LUCATenace V.Calimera A. | - |
| A compression-driven training framework for embedded deep neural networks / Grimaldi, M., Pugliese, F., Tenace, V., Calimera, A.. - (2018), pp. 45-50. (2018 Workshop on INTelligent Embedded Systems Architectures and Applications, INTESA 2018 ita 2018) [10.1145/3285017.3285021]. | 1-gen-2018 | Grimaldi M.PUGLIESE, FEDERICOTenace V.Calimera A. | - |
| Inferential Logic: A Machine Learning Inspired Paradigm for Combinational Circuits / Tenace, V., Calimera, A.. - (2018), pp. 149-154. (26th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018 Verona (ITA) 08-10 October 2018) [10.1109/VLSI-SoC.2018.8644808]. | 1-gen-2018 | Tenace V.Calimera A. | 08644808.pdf; VLSI-SOC_2018_paper_79.pdf |
| Multiplication by Inference using Classification Trees: A Case-Study Analysis / Rizzo, R.G., Tenace, V., Calimera, A.. - (2018), pp. 1-5. (IEEE International Symposium on Circuits and Systems (ISCAS) ) [10.1109/ISCAS.2018.8351206]. | 1-gen-2018 | Rizzo, Roberto GiorgioTenace, ValerioCalimera, Andrea | - |
| Activation-kernel extraction through machine learning / Tenace, V., Calimera, A.. - (2017), pp. 5-8. (1st New Generation of CAS, NGCAS 2017 ita 2017) [10.1109/NGCAS.2017.29]. | 1-gen-2017 | Tenace, ValerioCalimera, Andrea | - |
| Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies / Tenace, V., Calimera, A., Macii, E., Poncino, M.. - ELETTRONICO. - (2016), pp. 2897-2897. (2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 Montreal's Sheraton Centre, can 2016) [10.1109/ISCAS.2016.7539200]. | 1-gen-2016 | TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | 07539200.pdf |
| Graphene-PLA (GPLA): A compact and ultra-low power logic array architecture / Tenace, V., Calimera, A., Macii, E., Poncino, M.. - ELETTRONICO. - (2016), pp. 145-150. (26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016 usa 2016) [10.1145/2902961.2902970]. | 1-gen-2016 | TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | main.pdf; 2902961.2902970.pdf |
| Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits / Tenace, V., Calimera, A., Macii, E., Poncino, M.. - (2016), pp. 1-6. (24th Annual IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016 Tallin, Estonia 26-28 Settembre 2016) [10.1109/VLSI-SoC.2016.7753575]. | 1-gen-2016 | TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | vlsisoc2016_multi.pdf; 07753575.pdf |
| Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization / Miryala, S., Tenace, V., Calimera, A., Macii, E., Poncino, M., Amaru', L.G., De Micheli, G., Gaillardon, P.E.. - ELETTRONICO. - (2015), pp. 39-44. (Great Lakes Symposium on VLSI ) [10.1145/2742060.2742098]. | 1-gen-2015 | MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMOAMARU', LUCA GAETANO + | - |
| One-pass logic synthesis for graphene-based Pass-XNOR logic circuits / Tenace, V., Calimera, A., Macii, E., Poncino, M.. - ELETTRONICO. - (2015), pp. 1-6. (52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015 usa 2015) [10.1145/2744769.2744880]. | 1-gen-2015 | TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| Pass-XNOR Logic: A new Logic Style for P-N Junction based Graphene Circuits / Tenace, V., Calimera, A., Macii, E., Poncino, M.. - (2014). (DATE-14: ACM/IEEE Design, Automation and Test in Europe ). | 1-gen-2014 | TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| Quantifying the figures of merit of graphene-based adiabatic Pass-XNOR Logic (PXL) circuits / Tenace, V., Calimera, A., Macii, E., Poncino, M.. - (2014), pp. 1-4. (PRIME-14: IEEE Conference on Ph.D. Research in Microelectronics and Electronics ). | 1-gen-2014 | TENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO | - |
| Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation / Tenace, V., Miryala, S., Calimera, A., Macii, A., Macii, E., Poncino, M.. - (2012), pp. 1-6. (THERMINIC-12: IEEE International Workshop on Thermal Investigations of ICs and Systems Budapest September). | 1-gen-2012 | TENACE, VALERIOMIRYALA, SANDEEPCALIMERA, ANDREAMACII, AlbertoMACII, EnricoPONCINO, MASSIMO | - |
| NBTI effects on tree-like clock distribution networks / Wei, L., Miryala, S., Tenace, V., Calimera, A., Macii, E., Poncino, M.. - (2012), pp. 279-282. (GLSVLSI-12: IEEE/ACM Great Lakes symposium on VLSI Salt Lake City, Utah May 2012) [10.1145/2206781.2206849]. | 1-gen-2012 | MIRYALA, SANDEEPTENACE, VALERIOCALIMERA, ANDREAMACII, EnricoPONCINO, MASSIMO + | - |