statistiche ricercatore

Continente	#
EU - Europa	2.057
NA - Nord America	1.293
AS - Asia	236
SA - Sud America	7
OC - Oceania	3
Continente sconosciuto - Info sul continente non disponibili	2
Totale	3.598

Nazione	#
US - Stati Uniti d'America	1.284
IT - Italia	885
GB - Regno Unito	458
DE - Germania	281
FR - Francia	179
CN - Cina	86
UA - Ucraina	58
AT - Austria	38
KR - Corea	34
SG - Singapore	34
IE - Irlanda	28
TR - Turchia	28
BE - Belgio	27
CH - Svizzera	27
SE - Svezia	18
JO - Giordania	16
MY - Malesia	15
FI - Finlandia	14
NL - Olanda	11
CA - Canada	8
EU - Europa	7
IN - India	7
RU - Federazione Russa	6
ID - Indonesia	5
HK - Hong Kong	4
IR - Iran	4
AU - Australia	3
BY - Bielorussia	3
CL - Cile	3
EE - Estonia	3
HR - Croazia	3
JP - Giappone	3
BR - Brasile	2
IL - Israele	2
RO - Romania	2
AE - Emirati Arabi Uniti	1
AL - Albania	1
AR - Argentina	1
CO - Colombia	1
CZ - Repubblica Ceca	1
DK - Danimarca	1
HN - Honduras	1
LU - Lussemburgo	1
PK - Pakistan	1
PL - Polonia	1
SK - Slovacchia (Repubblica Slovacca)	1
TW - Taiwan	1
Totale	3.598

Nome	#
Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties	383
To Split or to Group: From Divide-and-Conquer to Sub-Task Sharing for Verifying Multiple Properties in Model Checking	324
Hardware Model Checking Competition 2014: An Analysis and Comparison of Model Checkers and Benchmarks	294
SAT solver management strategies in IC3: an experimental approach	271
Interpolation with Guided Refinement: revisiting incrementality in SAT-based Unbounded Model Checking	265
Test Time Minimization in Reconfigurable Scan Networks	258
Reducing Interpolant Circuit Size by Ad Hoc Logic Synthesis and SAT-Based Weakening	254
A 7/2-approximation algorithm for the Maximum Duo-Preservation String Mapping Problem	250
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification	245
Trading-off Incrementality and Dynamic Restart of Multiple Solvers in IC3	222
Interpolation-based learning as a mean to speed-up Bounded Model Checking	195
Logic Synthesis for Interpolant Circuit Compaction	142
Exploiting Boolean Satisfiability Solvers for High Performance Bit-Level Model Checking	134
Test of Reconfigurable Modules in Scan Networks	130
Reducing interpolant circuit size through SAT-based weakening	125
Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking	107
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification	25
Hardware Model Checking Algorithms and Techniques	24
Totale	3.648

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2019/2020	477	34	24	17	77	70	47	61	51	54	22	11	9
2020/2021	322	33	45	11	26	8	41	19	36	37	27	32	7
2021/2022	308	22	31	5	24	11	28	21	10	39	13	39	65
2022/2023	432	27	64	9	45	38	88	26	31	55	4	17	28
2023/2024	261	9	3	20	23	23	38	13	21	17	20	36	38
2024/2025	26	26	0	0	0	0	0	0	0	0	0	0	0
Totale													3.648

PORTO @ Archivio Istituzionale della Ricerca