PORTO @ Archivio Istituzionale della Ricerca

PALENA, MARCO
 Distribuzione geografica
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Continente #
NA - Nord America 146
EU - Europa 119
AS - Asia 11
SA - Sud America 2
Totale 278
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Nazione #
US - Stati Uniti d'America 138
IT - Italia 85
DE - Germania 11
IE - Irlanda 9
CA - Canada 8
GB - Regno Unito 6
CN - Cina 5
AE - Emirati Arabi Uniti 2
CL - Cile 2
FR - Francia 2
ID - Indonesia 2
IN - India 2
NL - Olanda 2
CZ - Repubblica Ceca 1
NO - Norvegia 1
RU - Federazione Russa 1
SE - Svezia 1
Totale 278
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Città #
Torino 34
Houston 31
Santa Cruz 16
Ann Arbor 14
Dublin 9
Fairfield 8
Turin 7
Buffalo 6
Seattle 6
Toronto 6
Bremen 5
San Diego 4
Ashburn 3
Carignano 3
San Donato Milanese 3
Wilmington 3
Cambridge 2
Costabissara 2
Cuneo 2
Jinan 2
Milan 2
Ottawa 2
Triggiano 2
Vicenza 2
Villastellone 2
Woodbridge 2
Wuhan 2
Andover 1
Augusta 1
Beijing 1
Bengaluru 1
Boulder 1
Cheyenne 1
Clearwater 1
Cloppenburg 1
Dallas 1
Genova 1
Goldenstedt 1
Groningen 1
Guwahati 1
Jacksonville 1
Lake Forest 1
Los Angeles 1
Miami 1
Norwalk 1
Palo Alto 1
Rome 1
San Francisco 1
San Mateo 1
Santiago 1
Scottsdale 1
Stavanger 1
Stuttgart 1
Sunnyvale 1
University Park 1
Wierden 1
Yellow Springs 1
Totale 210
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Nome #
Reducing Interpolant Circuit Size by Ad Hoc Logic Synthesis and SAT-Based Weakening, file e384c42f-3256-d4b2-e053-9f05fe0a1d67 103
Test Time Minimization in Reconfigurable Scan Networks, file e384c42f-32d5-d4b2-e053-9f05fe0a1d67 90
Test of Reconfigurable Modules in Scan Networks, file e384c430-335a-d4b2-e053-9f05fe0a1d67 59
Fast Cone-Of-Influence Computation and Estimation in Problems with Multiple Properties, file e384c42e-a869-d4b2-e053-9f05fe0a1d67 9
Hardware Model Checking Competition 2014: An Analysis and Comparison of Model Checkers and Benchmarks, file e384c42e-ad14-d4b2-e053-9f05fe0a1d67 8
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification, file e384c432-d1f0-d4b2-e053-9f05fe0a1d67 6
Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking, file 4ac6a48f-eb82-484f-92e8-734e62bd612d 4
Test Time Minimization in Reconfigurable Scan Networks, file e384c42f-7b53-d4b2-e053-9f05fe0a1d67 3
Logic Synthesis for Interpolant Circuit Compaction, file e384c431-f0f0-d4b2-e053-9f05fe0a1d67 3
To Split or to Group: From Divide-and-Conquer to Sub-Task Sharing for Verifying Multiple Properties in Model Checking, file e384c432-638c-d4b2-e053-9f05fe0a1d67 3
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification, file 5146edf5-ce48-44b7-9bbf-f082c83a24ac 2
Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking, file 619e9dd4-f974-453f-bf68-a61758eaea9c 2
Exploiting Boolean Satisfiability Solvers for High Performance Bit-Level Model Checking, file e384c42f-99a5-d4b2-e053-9f05fe0a1d67 1
Reducing Interpolant Circuit Size by Ad Hoc Logic Synthesis and SAT-Based Weakening, file e384c432-304b-d4b2-e053-9f05fe0a1d67 1
Totale 294
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Categoria #
all - tutte 421
article - articoli 125
book - libri 0
conference - conferenze 295
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 841
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/20191 0 0 0 0 0 0 0 0 0 0 0 1
2019/202013 0 0 3 0 3 1 0 1 4 0 1 0
2020/202171 8 4 3 6 9 10 4 7 2 6 7 5
2021/2022121 15 6 7 30 15 9 9 4 0 4 17 5
2022/202361 2 4 14 8 9 14 7 3 0 0 0 0
2023/20243 0 0 0 0 0 0 0 1 0 2 0 0
Totale 294