A Novel Node- and Layout-Aware Radiation-Hardened 7 nm D Flip-Flop

Technology scaling has increased the vulnerability of sequential logic to radiation-induced single-event upsets (SEUs), motivating radiation-hardened flip-flop designs with low overhead. This paper presents a radiation-hardened D flip-flop (DFF) based on a node- and layout-aware hardening methodology. By selectively reinforcing the most sensitive internal nodes instead of uniformly hardening the entire circuit, the proposed design effectively mitigates SEUs with limited performance penalty. Compared with a standard DFF, the hardened design significantly lifts the SEU resilience while incurs modest cost (area 1.05×, power 1.56×, and delay 1.51×) and achieves a reduced Area–Power–Delay Product (APDP) of 2.47×. When applied in a triple modular redundancy (TMR) system, the proposed DFF reduces the system-level error rate from 0.32% to 0.068% (approximately 21% of the baseline), demonstrating its effectiveness for radiation-tolerant systems.