Quantum Key Distribution (QKD) is increasingly adopted in security-critical links and future scenarios will include also space applications where radiation-induced faults can compromise the correctness and availability of the protocol. This risk is amplified on SRAM-based FPGAs, where configuration upsets can alter circuit behavior. Through this paper, we present a robust, heterogeneous FPGA/SoC platform to validate the reliability of QKD sifting on commercial off-the-shelf hardware. A lightweight RISC-V processor supervise the entire procedure, while the sifting accelerator is coupled with a lightweight monitoring unit to detects faults and triggers error correction through partial reconfiguration. The platform has been implemented on AMD ZCU102 UltraScale+ development boards and evaluated through fault injections. The adopted mitigation techniques allows downtime reduction by about 12000 × and lowers the sifting-module error rate by around 2%.
Robust Quantum Communication for Space Systems Through an Heterogeneous RISC-V based FPGA/SoC Platform / Cora, G., Bardpareh, A.A., Lobo, G.M.J.F., De Sio, C., Azimi, S., Stanco, A., Sterpone, L.. - (2026), pp. 67-70. (23rd ACM International Conference on Computing Frontiers, CF 2026 Catania (ITA) May 19 - 21, 2026) [10.1145/3801487.3801825].
Robust Quantum Communication for Space Systems Through an Heterogeneous RISC-V based FPGA/SoC Platform
Cora G.;De Sio C.;Azimi S.;Sterpone L.
2026
Abstract
Quantum Key Distribution (QKD) is increasingly adopted in security-critical links and future scenarios will include also space applications where radiation-induced faults can compromise the correctness and availability of the protocol. This risk is amplified on SRAM-based FPGAs, where configuration upsets can alter circuit behavior. Through this paper, we present a robust, heterogeneous FPGA/SoC platform to validate the reliability of QKD sifting on commercial off-the-shelf hardware. A lightweight RISC-V processor supervise the entire procedure, while the sifting accelerator is coupled with a lightweight monitoring unit to detects faults and triggers error correction through partial reconfiguration. The platform has been implemented on AMD ZCU102 UltraScale+ development boards and evaluated through fault injections. The adopted mitigation techniques allows downtime reduction by about 12000 × and lowers the sifting-module error rate by around 2%.| File | Dimensione | Formato | |
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3801487.3801825.pdf
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https://hdl.handle.net/11583/3013171
