Automatic Enhancement of Cell Models to Enable Conditional Stuck-at Fault Simulation and Pattern Generation

Automatic test pattern generation (ATPG) and fault simulation methods for stuck-at faults (SAFs) cannot accurately capture the behavior of conditional stuck-at faults (CSAFs), which manifest only under specific input combinations. To manage such conditional faults using conventional stuck-at fault simulators and test pattern generators, we propose a methodology that embeds conditional fault behavior directly into the logic description of standard cells. The method operates on conditional stuck-at fault models, which define the output variations of a cell in the presence of specific conditional faults for all input stimuli. Each cell model is translated into a Boolean equation that represent the internal logic conditions required to activate the associated faults. This equation is then integrated into the functional description of the standard cell, without modifying its primary inputs, outputs, or intended behavior. As a result, the augmented standard cell library can reproduce the effects of conditional stuck-at faults while remaining compatible with existing fault simulation and ATPG tools. The proposed method incurs negligible application time, and experiments on several benchmark circuits and cores demonstrate reasonable overhead in test pattern count and CPU time.