A Novel Layout-Circuit Co-Design Framework for Radiation Hardening in Nanoscale Technology

Electronic components in space are vulnerable to radiation-induced Single-Event Effects (SEEs). This work proposes a mitigation methodology combining layout- and circuit-level analysis with targeted hardening. First, radiation induced charge deposition through the device stack is characterized and converted into equivalent transient current pulses, yielding Single-Event Transient (SET) profiles for the given technology and topology. These profiles drive circuitlevel fault injection to identify sensitive nodes, which are selectively hardened via layout modifications. Applied to a 15 nm 2:1 multiplexer, the approach improves SEE resilience with minimal delay, power, and area penalties. The hardened design increases the error threshold current by 5.69 times and reduces SET duration by ~39%.