On-Hardware Resilience Analysis of DPU-Accelerated CNNs on FPGA-Based Systems

In recent years, Reconfigurable SoCs have emerged as a high-performance solution for embedded systems, addressing the increasing complexity of neural networks, balancing performance, cost, and adaptability. Flexible hardware accelerators, such as AMD’s Deep Learning Processing Units (DPUs), enable efficient computation across various domains, including safety-critical applications. However, soft errors remain a significant reliability concern, especially in harsh environments like space, where radiationinduced corruption of configuration memory poses a significant threat to FPGA-based systems. Most research on the reliability and robustness of deep learning models against soft errors has focused on application-level analyses, with comparatively little attention paid to architectural hardware faults. This paper introduces a resilience evaluation framework targeting AMD’s state-of-the-art DPU, comparing traditional application-level fault injection with hardware-aware fault injection performed on an actual hardware platform, a Kria KV260. Applying this methodology, we evaluated fourteen different deep neural network architectures and demonstrated that hardware-aware fault injections reveal critical vulnerabilities that applicationonly approaches fail to detect. Moreover, we investigated the source of different faults at the hardware level, enabling the identification of architectural resources that are more susceptible to errors. These insights are valuable to support the development of more robust deployment strategies and mitigation techniques tailored to FPGA-based deep learning accelerators.