From Structural Test Escapes to Silent Data Errors: A preliminary analysis

IIn recent years, the observed Failure-in-Time (FIT) rates of semiconductor devices in data center fleets by cloud service providers have drastically increased, pinpointing that defective devices are escaping during manufacturing tests. Although semiconductor manufacturers minimize FIT rates of their devices, the exponential deployment at scale, combined with growing design complexity and increasing transistor density, results in a non-negligible number of defective devices in server fleets. High-end processors undergo different manufacturing test phases to ensure low defect-part-per-million (DPPM) of shipped defective devices. However, it is always difficult, if not impossible, to cover the full spectrum of all possible defects in a device. This paper proposes a grading methodology for manufacturing test escapes of a permanent nature, such as Stuck-At faults, Transition Delay faults, and Small Delay Faults, that would be very likely to produce Silent Data Errors (SDEs). The proposed methodology combines several structural measurements that describe a fault's likelihood to create a silent data error. If the faults that are at high risk of being SDE can be identified early in the product lifecycle, design decisions can be made to prevent these faults from actually creating silent data errors when the device is deployed. Experimental results are carried out on arithmetic modules used frequently in High Performance Computing.