Recently, efficiently deploying deep learning solutions on the edge has received increasing attention. New platforms are emerging to support the increasing demand for flexibility and high performance. In this work, we explore the efficient mapping of convolutional layers on an open-hardware, low-power Coarse-Grain Reconfigurable Array (CGRA), namely OpenEdgeCGRA. We explore both direct implementations of convolution and solutions that transform it into a matrix multiplication through an Im2col transformation and experiment with various tensor parallelism axes. We show that for this hardware target, direct convolution, coupled with weight parallelism, reaches the best latency and energy efficiency, outperforming a pure CPU implementation by 3.4× and 9.9× in terms of energy and latency, respectively.

Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA / Carpentieri, Nicolò; Sapriza, Juan; Schiavone, Davide; JAHIER PAGLIARI, Daniele; Atienza, David; Martina, Maurizio; Burrello, Alessio. - (2024), pp. 67-70. (Intervento presentato al convegno CF '24: 21st ACM International Conference on Computing Frontiers tenutosi a Ischia (ITA) nel May 7 - 9, 2024) [10.1145/3637543.3652875].

Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA

Daniele Jahier Pagliari;Maurizio Martina;Alessio Burrello
2024

Abstract

Recently, efficiently deploying deep learning solutions on the edge has received increasing attention. New platforms are emerging to support the increasing demand for flexibility and high performance. In this work, we explore the efficient mapping of convolutional layers on an open-hardware, low-power Coarse-Grain Reconfigurable Array (CGRA), namely OpenEdgeCGRA. We explore both direct implementations of convolution and solutions that transform it into a matrix multiplication through an Im2col transformation and experiment with various tensor parallelism axes. We show that for this hardware target, direct convolution, coupled with weight parallelism, reaches the best latency and energy efficiency, outperforming a pure CPU implementation by 3.4× and 9.9× in terms of energy and latency, respectively.
2024
979-8-4007-0492-5
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2991606