Today, advances in scientific and embedded computing and the incredible proliferation of machine learning algorithms take advantage of specialized hardware accelerators to provide exceptional performance and good accuracy. In some safety-critical applications like autonomous robotics, healthcare, and automotive, crucial mathematical operations such as convolutions are often efficiently mapped in hardware as Matrix-Vector(MxV) and Matrix-Matrix (MxM) multiplications. Moreover, sophisticated sparsity algorithms aim to improve performance and power consumption. Unfortunately, technology scaling trends may increase the proliferation of faults on hardware during the in-field operation, so there is a rising interest in the reliability assessment and analysis of sparsity-based accelerators. This work evaluates the impact of soft errors (bit-flips) on sparse-matrix dense-vector multiplication (SpMV) cores for safety-critical tactile sensing applications by resorting to a High-Level Synthesis (HLS) strategy. The experiments are performed on an open-source streaming SpMV core using the Compressed Sparse Row (CSR) format when processing characteristic medium-size sparse matrices (100x100 and 494x494). Our results indicate that data-path pipeline registers in the (SpMV) core are resilient to transient faults (< 1.3% of observed corruption effects), while large magnitude errors can be associated with the type of sparse matrix describing the system (e.g., number of non-zero values) and the type and features of the input vector sensor.

Analyzing the Reliability of Stream Sparse Matrix-Vector Multiplication Accelerators: A High-Level Approach / Pinto-Salamanca, María L.; Rodriguez Condia, Josie Esteban; Hidalgo-López, José A.; Perez Holguin, Wilson Javier. - ELETTRONICO. - (2024), pp. 1-4. (Intervento presentato al convegno 2024 IEEE 25th Latin American Test Symposium (LATS) tenutosi a Maceio (BRA) nel 09-12 April 2024) [10.1109/lats62223.2024.10534624].

Analyzing the Reliability of Stream Sparse Matrix-Vector Multiplication Accelerators: A High-Level Approach

Rodriguez Condia, Josie Esteban;
2024

Abstract

Today, advances in scientific and embedded computing and the incredible proliferation of machine learning algorithms take advantage of specialized hardware accelerators to provide exceptional performance and good accuracy. In some safety-critical applications like autonomous robotics, healthcare, and automotive, crucial mathematical operations such as convolutions are often efficiently mapped in hardware as Matrix-Vector(MxV) and Matrix-Matrix (MxM) multiplications. Moreover, sophisticated sparsity algorithms aim to improve performance and power consumption. Unfortunately, technology scaling trends may increase the proliferation of faults on hardware during the in-field operation, so there is a rising interest in the reliability assessment and analysis of sparsity-based accelerators. This work evaluates the impact of soft errors (bit-flips) on sparse-matrix dense-vector multiplication (SpMV) cores for safety-critical tactile sensing applications by resorting to a High-Level Synthesis (HLS) strategy. The experiments are performed on an open-source streaming SpMV core using the Compressed Sparse Row (CSR) format when processing characteristic medium-size sparse matrices (100x100 and 494x494). Our results indicate that data-path pipeline registers in the (SpMV) core are resilient to transient faults (< 1.3% of observed corruption effects), while large magnitude errors can be associated with the type of sparse matrix describing the system (e.g., number of non-zero values) and the type and features of the input vector sensor.
2024
979-8-3503-6555-9
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2989177