This paper describes an architecture-modulable FPGA framework comprising synthesis, mapping, place and route, and bitstream analysis and mitigation for circuits mapped on FPGAs suitable for aerospace applications. The framework has several benefits, including analysis of soft-error effects and comparison between different vendors and parts, compatibility with commercial and radiation-hardened FPGA, and the ability to individuate single point of failure and embeds different mitigation strategies such as Triple Modular Redundancy (TMR) and Single Event Transient (SET) filtering at the synthesis or the place and route level. In this work, we provide the description of the framework and the radiation-effects analysis and mitigation on a set of benchmark circuits implemented using the most recent FPGA devices families for aerospace such as AMD Xilinx Ultrascale, NanoXplore NG-Medium, Microchip Radiation-Tolerant ProASIC3, and Radiation-Tolerant G4. Finally, we present a comparative analysis of a benchmark circuit's performance and radiation sensitivity mapped on the different FPGA device manufacturers.
A Framework for Uniformly Analyze and Mitigate Radiation-effects on FPGAs for Aerospace / Sterpone, Luca; Azimi, Sarah; DE SIO, Corrado. - (2023), pp. 257-262. (Intervento presentato al convegno 20th ACM International Conference on Computing Frontiers tenutosi a Bologna (IT) nel May 9 - 11, 2023) [10.1145/3587135.3592768].
A Framework for Uniformly Analyze and Mitigate Radiation-effects on FPGAs for Aerospace
Luca Sterpone;Sarah Azimi;Corrado De Sio
2023
Abstract
This paper describes an architecture-modulable FPGA framework comprising synthesis, mapping, place and route, and bitstream analysis and mitigation for circuits mapped on FPGAs suitable for aerospace applications. The framework has several benefits, including analysis of soft-error effects and comparison between different vendors and parts, compatibility with commercial and radiation-hardened FPGA, and the ability to individuate single point of failure and embeds different mitigation strategies such as Triple Modular Redundancy (TMR) and Single Event Transient (SET) filtering at the synthesis or the place and route level. In this work, we provide the description of the framework and the radiation-effects analysis and mitigation on a set of benchmark circuits implemented using the most recent FPGA devices families for aerospace such as AMD Xilinx Ultrascale, NanoXplore NG-Medium, Microchip Radiation-Tolerant ProASIC3, and Radiation-Tolerant G4. Finally, we present a comparative analysis of a benchmark circuit's performance and radiation sensitivity mapped on the different FPGA device manufacturers.File | Dimensione | Formato | |
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https://hdl.handle.net/11583/2981725