PORTO @ 
Archivio Istituzionale della Ricerca
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishSystem-level test (SLT) is gaining in importance in modern test flows. This paper summarizes recent industrial findings from three companies and discusses some of the still open questions. The first two reports focus on the optimization potentials due to defect coverage overlaps between SLT and other test insertions. Results observed on approximately 20 million manufactured 28nm and 40nm automotive system-on-chip (SoC) designs are reported. Costs and benefits of SLT are discussed and the potentials of a test results analytics platform are identified. The third report explores the role of marginalities among SLT fails. The post-silicon investigation of a CPU block in a 7nm 5G mobile SoC product aims at achieving a better understanding, whose fails are due to random variations versus systematic factors.
System-Level Test: State of the Art and Challenges / Appello, D.; Chen, H. H.; Sauer, M.; Polian, I.; Bernardi, P.; Reorda, M. S.. - (2021), pp. 1-7. ((Intervento presentato al convegno 27th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2021 nel 2021 [10.1109/IOLTS52814.2021.9486708].
| Titolo: | System-Level Test: State of the Art and Challenges | |
| Autori: | ||
| Data di pubblicazione: | 2021 | |
| Abstract: | System-level test (SLT) is gaining in importance in modern test flows. This paper summarizes rece...nt industrial findings from three companies and discusses some of the still open questions. The first two reports focus on the optimization potentials due to defect coverage overlaps between SLT and other test insertions. Results observed on approximately 20 million manufactured 28nm and 40nm automotive system-on-chip (SoC) designs are reported. Costs and benefits of SLT are discussed and the potentials of a test results analytics platform are identified. The third report explores the role of marginalities among SLT fails. The post-silicon investigation of a CPU block in a 7nm 5G mobile SoC product aims at achieving a better understanding, whose fails are due to random variations versus systematic factors. | |
| ISBN: | 978-1-6654-3370-9 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| System-Level_Test_State_of_the_Art_and_Challenges.pdf | 2a Post-print versione editoriale / Version of Record | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2939957
Copyright © 2022