Vias are critical for digital circuit manufacturing, as they represent a common defect location, and a general DfM rule suggests replicating every instance for redundancy. When this is not achievable, a mandatory requirement is that the remaining single vias must be tested. We propose an automated method for generating tests and accurately evaluating test coverage of such defects, ready for use in any digital implementation flow and for integration within EDA tools, and also providing a useful quality metric. A prototype tool implementation and experimental results for an industrial case study are presented.

On the test of single via related defects in digital VLSI designs / Mirabella, N.; Ricci, M.; Grosso, M.. - ELETTRONICO. - (2020), pp. 1-6. ((Intervento presentato al convegno 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020 tenutosi a Serbia nel 2020 [10.1109/DDECS50862.2020.9095717].

On the test of single via related defects in digital VLSI designs

Mirabella N.;Grosso M.
2020

Abstract

Vias are critical for digital circuit manufacturing, as they represent a common defect location, and a general DfM rule suggests replicating every instance for redundancy. When this is not achievable, a mandatory requirement is that the remaining single vias must be tested. We propose an automated method for generating tests and accurately evaluating test coverage of such defects, ready for use in any digital implementation flow and for integration within EDA tools, and also providing a useful quality metric. A prototype tool implementation and experimental results for an industrial case study are presented.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/2920374