Leakage discharge currents represent one of the most detrimental factors for the maximum hold time in analog sample-and-hold circuits. Apart from the obvious passive solution of enlarging the sampling capacitor, alternatives based on active circuits have been proposed. We focus here on an existing solution which has proven to be effective in reducing the leakage discharge, hence extending the hold time, by a factor of 20. Being based on a feedback circuit built around the hold capacitor, it is paramount to understand its stability properties. This work tries to close the gap by analyzing the closed-loop stability of the nominal circuit. Classical control systems techniques are employed to thoroughly analyze the dynamic behaviour of the feedback circuit, highlighting the detrimental effect of device mismatches.

Stability and mismatch robustness of a leakage current cancellation technique / Paolino, C.; Pareschi, F.; Rovatti, R.; Setti, G.. - STAMPA. - 2021:(2021). (Intervento presentato al convegno 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 tenutosi a Daegu, Corea del Sud [virtual] nel May 22-28, 2021) [10.1109/ISCAS51556.2021.9401430].

Stability and mismatch robustness of a leakage current cancellation technique

Paolino C.;Pareschi F.;Setti G.
2021

Abstract

Leakage discharge currents represent one of the most detrimental factors for the maximum hold time in analog sample-and-hold circuits. Apart from the obvious passive solution of enlarging the sampling capacitor, alternatives based on active circuits have been proposed. We focus here on an existing solution which has proven to be effective in reducing the leakage discharge, hence extending the hold time, by a factor of 20. Being based on a feedback circuit built around the hold capacitor, it is paramount to understand its stability properties. This work tries to close the gap by analyzing the closed-loop stability of the nominal circuit. Classical control systems techniques are employed to thoroughly analyze the dynamic behaviour of the feedback circuit, highlighting the detrimental effect of device mismatches.
2021
978-1-7281-9201-7
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2918012