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EnglishThis paper proposes a prototype of a Spread Spectrum Clock Generator which is the first known specifically meant for 3 GHz Serial ATA-II applications. The modulation is obtained from a fractional PLL which employs a Delta-Sigma modulator. A further innovative aspect of our work is that our prototype takes advantage of a chaotic PAM as driving signal, instead a triangular signal as in all spread spectrum generators proposed in literature for SATA-II. In this way we avoid the periodicity of the modulated clock, completely flattening the peaks in the power spectral density. The circuit prototype has been designed n 0.13 μm CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz. The chip active area is 0.27×0.78 mm2 and the power consumption is as low as 14.7 mW. © 2008 IEEE.
A 3 GHz spread spectrum clock generator for SATA applications using chaotic PAM modulation / Pareschi, F.; Setti, G.; Rovatti, R.. - STAMPA. - (2008), pp. 451-454. ((Intervento presentato al convegno IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 tenutosi a San Jose, CA, usa nel 2008 [10.1109/CICC.2008.4672118].
| Titolo: | A 3 GHz spread spectrum clock generator for SATA applications using chaotic PAM modulation | |
| Autori: | ||
| Data di pubblicazione: | 2008 | |
| Abstract: | This paper proposes a prototype of a Spread Spectrum Clock Generator which is the first known spe...cifically meant for 3 GHz Serial ATA-II applications. The modulation is obtained from a fractional PLL which employs a Delta-Sigma modulator. A further innovative aspect of our work is that our prototype takes advantage of a chaotic PAM as driving signal, instead a triangular signal as in all spread spectrum generators proposed in literature for SATA-II. In this way we avoid the periodicity of the modulated clock, completely flattening the peaks in the power spectral density. The circuit prototype has been designed n 0.13 μm CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz. The chip active area is 0.27×0.78 mm2 and the power consumption is as low as 14.7 mW. © 2008 IEEE. | |
| ISBN: | 978-1-4244-2018-6 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| 116.pdf | Editorial Version | 2a Post-print versione editoriale / Version of Record | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
| CICC2008-pll4g.pdf | Author version of the Paper | 2. Post-print / Author's Accepted Manuscript | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri |
http://hdl.handle.net/11583/2850187
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