Since frame resolution of modern video streams is rapidly growing, the need for more complex and efficient video compression methods arises. H.265/HEVC represents the state of the art in video coding standard. Its architecture is however not completely standardized, as many parts are only described at software level to allow the designer to implement new compression techniques. This paper presents an innovative hardware architecture for the Steerable Discrete Cosine Transform (SDCT), which has been recently embedded into the HEVC standard, providing better compression ratios. Such technique exploits directional DCT using basis having different orientation angles, leading to a sparser representation which translates to an improved coding efficiency. The final design is able to work at a frequency of 188 MHZ, reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60 Hz, which is one of the best resolutions supported by HEVC.

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT) / Sole, Luigi; Peloso, Riccardo; Capra, Maurizio; Ruo Roch, Massimo; Masera, Guido; Martina, Maurizio. - ELETTRONICO. - 627:(2020), pp. 137-143. ((Intervento presentato al convegno ApplePies Applications in Electronics Pervading Industry, Environment and Society tenutosi a Pisa nel September 11-13, 2019 [10.1007/978-3-030-37277-4_16].

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT)

Peloso, Riccardo;Capra, Maurizio;Ruo Roch, Massimo;Masera, Guido;Martina, Maurizio
2020

Abstract

Since frame resolution of modern video streams is rapidly growing, the need for more complex and efficient video compression methods arises. H.265/HEVC represents the state of the art in video coding standard. Its architecture is however not completely standardized, as many parts are only described at software level to allow the designer to implement new compression techniques. This paper presents an innovative hardware architecture for the Steerable Discrete Cosine Transform (SDCT), which has been recently embedded into the HEVC standard, providing better compression ratios. Such technique exploits directional DCT using basis having different orientation angles, leading to a sparser representation which translates to an improved coding efficiency. The final design is able to work at a frequency of 188 MHZ, reaching a throughput of 3.00 GSample/s. In particular, this architecture supports 8k UltraHigh Definition (UHD) (7680 × 4320) with a frame rate of 60 Hz, which is one of the best resolutions supported by HEVC.
978-3-030-37276-7
978-3-030-37277-4
File in questo prodotto:
File Dimensione Formato  
main.pdf

embargo fino al 21/03/2021

Tipologia: 2. Post-print / Author's Accepted Manuscript
Licenza: PUBBLICO - Tutti i diritti riservati
Dimensione 297.92 kB
Formato Adobe PDF
297.92 kB Adobe PDF Visualizza/Apri
Sole2020_Chapter_VLSIArchitecturesForTheSteerab.pdf

non disponibili

Tipologia: 2a Post-print versione editoriale / Version of Record
Licenza: Non Pubblico - Accesso privato/ristretto
Dimensione 335.64 kB
Formato Adobe PDF
335.64 kB Adobe PDF   Visualizza/Apri   Richiedi una copia
Pubblicazioni consigliate

Caricamento pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2847345