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EnglishA fully synthesizable ADC architecture is proposed for low-end current sensing applications. Being based on standard cells and designed with a fully-automated flow, the proposed ADC allows very low area, digital-like scaling across CMOS technology generations, technology and design portability, minimal design effort, and immersed-in logic design (i.e., low integration effort), compared to traditional analog-intensive designs. In addition, it allows direct current readout without requiring a transresistance stage. Testchip measurements show a 5-nA to 1-μA input range, 6.7-bit ENOB and 2.2-kS/s sample rate, at 940-nW power and 4, 580-μm2 area. To the best of the authors' knowledge, this testchip is the first demonstration of a fully-synthesizable input-current ADC. Along with the analysis of the specific limitations of the presented demonstration, this work aims to pave the way for a new class of current-input ADCs that can be designed and integrated with logic within hours, and occupy a silicon area in the order of 10kgates.
Fully-synthesizable current-input ADCs for ultra-low area and minimal design effort / Aiello, O.; Crovetti, P.; Sharma, A.; Alioto, M.. - ELETTRONICO. - (2019), pp. 715-718. ((Intervento presentato al convegno 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 tenutosi a ita nel 2019 [10.1109/ICECS46596.2019.8964789].
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| Titolo: | Fully-synthesizable current-input ADCs for ultra-low area and minimal design effort | |
| Autori: | ||
| Data di pubblicazione: | 2019 | |
| Abstract: | A fully synthesizable ADC architecture is proposed for low-end current sensing applications. Bein...g based on standard cells and designed with a fully-automated flow, the proposed ADC allows very low area, digital-like scaling across CMOS technology generations, technology and design portability, minimal design effort, and immersed-in logic design (i.e., low integration effort), compared to traditional analog-intensive designs. In addition, it allows direct current readout without requiring a transresistance stage. Testchip measurements show a 5-nA to 1-μA input range, 6.7-bit ENOB and 2.2-kS/s sample rate, at 940-nW power and 4, 580-μm2 area. To the best of the authors' knowledge, this testchip is the first demonstration of a fully-synthesizable input-current ADC. Along with the analysis of the specific limitations of the presented demonstration, this work aims to pave the way for a new class of current-input ADCs that can be designed and integrated with logic within hours, and occupy a silicon area in the order of 10kgates. | |
| ISBN: | 978-1-7281-0996-1 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| PID6174479.pdf | Post-print non editoriale | 2. Post-print / Author's Accepted Manuscript | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri |
| Crovetti-Fully-synthesizable-pdf.pdf | 2a Post-print versione editoriale / Version of Record | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2816536
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