Assessing Test Procedure Effectiveness for Power Devices

The use of power electronics in safety-critical applications requires specific test techniques for these devices. In particular, it is important to adopt some metric for assessing the quality of a given Test Procedure, e.g., by introducing fault models allowing to compute a Fault Coverage (FC) figure for the analog electronics, as already successfully done for digital electronics. In the digital domain the scientific and industrial community has adopted some fault models (e.g., stuck-at) for permanent faults. The use of this model (and others) allows to establish a priori a finite list of possible faults to be considered, to study their effects during the test (i.e., to determine which of these faults are detected) and during the operational phase (e.g., to perform FMEA), and to generate suitable test procedures targeting them. In the analog domain such widely accepted fault models do not exist, although some fault models have been recently proposed and new commercial tools have been introduced to assess the analog fault coverage. The goal of this paper is to focus on power devices and use a possible fault model for analog and mixed-signal circuits resorting to the device equivalent model for evaluating the Power Fault Coverage (PFC) achieved by a test procedure for the Power Device Under Test (PDUT).