This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.

Role of parasitic capacitances in power MOSFET turn-on switching speed limits: a SiC case study / Cittanti, Davide; Iannuzzo, Francesco; Hoene, Eckart; Klein, Kirill. - ELETTRONICO. - (2017), pp. 1387-1394. (Intervento presentato al convegno 9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017 tenutosi a USA nel 2017) [10.1109/ECCE.2017.8095952].

### Role of parasitic capacitances in power MOSFET turn-on switching speed limits: a SiC case study

#### Abstract

This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.
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Utilizza questo identificativo per citare o creare un link a questo documento: `https://hdl.handle.net/11583/2711483`
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