Abstract— The increasing complexity of electronic components based on microprocessors and their use in safety-critical application – like automotive devices – make reliability a critical aspect. During the life cycle of such products, it is needed to periodically check whether the processor cores are working correctly. In most cases, this task is performed by running short, fast and specialized test programs that satisfies in-field testing requirements. This paper proposes a method that exploits an evolutionary-computation technique for the automatic compaction of these in-field oriented test programs. The aim of the proposed approach is twofold: reduce execution time and memory occupation, while maintaining the fault coverage of the original test program. Experimental results gathered on miniMIPS, a freely available 5-stage pipelined processor core, demonstrate the effectiveness of the proposed technique.

An Evolutionary Approach for Test Program Compaction / Cantoro, Riccardo; Gaudesi, Marco; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schiavone, P.; Squillero, Giovanni. - STAMPA. - 1:(2015), pp. 1-6. ((Intervento presentato al convegno 16th Latin-American Test Symposium tenutosi a Puerto Vallarta, Mexico nel March 25-27 [10.1109/LATW.2015.7102406].

An Evolutionary Approach for Test Program Compaction

CANTORO, RICCARDO;GAUDESI, MARCO;SANCHEZ SANCHEZ, EDGAR ERNESTO;SQUILLERO, Giovanni
2015

Abstract

Abstract— The increasing complexity of electronic components based on microprocessors and their use in safety-critical application – like automotive devices – make reliability a critical aspect. During the life cycle of such products, it is needed to periodically check whether the processor cores are working correctly. In most cases, this task is performed by running short, fast and specialized test programs that satisfies in-field testing requirements. This paper proposes a method that exploits an evolutionary-computation technique for the automatic compaction of these in-field oriented test programs. The aim of the proposed approach is twofold: reduce execution time and memory occupation, while maintaining the fault coverage of the original test program. Experimental results gathered on miniMIPS, a freely available 5-stage pipelined processor core, demonstrate the effectiveness of the proposed technique.
978-146736710-3
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2588571
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