Electronic systems are increasingly used for safety-critical applications, where the effects of faults must be taken under control and hopefully avoided. For this purpose, test of manufactured devices is particularly important, both at the end of the production line and during the operational phase. This paper describes a method to test the logic implementing the Branch Prediction Unit in pipelined and superscalar processors when this follows the Branch Target Buffer (BTB) architecture; the proposed approach is functional, i.e., it is based on forcing the processor to execute a suitably devised test program and observing the produced results. Experimental results are provided on the DLX processor, showing that the method can achieve a high value of stuck-at fault coverage while also testing the memory in the BTB

On the functional test of the BTB logic in pipelined and superscalar processors / Changdao, D.; Graziano, Mariagrazia; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Zamboni, Maurizio; Zhifan, N.. - (2013), pp. 1-6. (Intervento presentato al convegno Test Workshop (LATW), 2013 14th Latin American tenutosi a Cordoba, Argentina nel 2013) [10.1109/LATW.2013.6562677].

On the functional test of the BTB logic in pipelined and superscalar processors

GRAZIANO, MARIAGRAZIA;SANCHEZ SANCHEZ, EDGAR ERNESTO;SONZA REORDA, Matteo;ZAMBONI, Maurizio;
2013

Abstract

Electronic systems are increasingly used for safety-critical applications, where the effects of faults must be taken under control and hopefully avoided. For this purpose, test of manufactured devices is particularly important, both at the end of the production line and during the operational phase. This paper describes a method to test the logic implementing the Branch Prediction Unit in pipelined and superscalar processors when this follows the Branch Target Buffer (BTB) architecture; the proposed approach is functional, i.e., it is based on forcing the processor to execute a suitably devised test program and observing the produced results. Experimental results are provided on the DLX processor, showing that the method can achieve a high value of stuck-at fault coverage while also testing the memory in the BTB
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2510685
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