On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

Very Long Instruction Word (VLIW) processors are increasingly employed in a large range of embedded signal processing applications, mainly due to their ability to provide high performances with reduced clock rate and power consumption. At the same time, there is an increasing request for efficient and optimal test techniques able to detect permanent faults in VLIW processors. Software-Based Self-Test (SBST) methods are a consolidated and effective solution to detect faults into a processor both at the end of the production phase or during the operational life; however, when traditional SBST techniques are applied to VLIW processors, they may result to be ineffective (especially in terms of size and duration), due to their inabilitytoexploittheparallelismintrinsicinthesearchitectures. In this paper we present a new method for the automatic generation of efficient test programs specifically oriented to VLIW processors. The method starts from existing test programs based on generic SBST algorithms and automatically generates effective test programs able to reach the same fault coverage, while minimizing the test duration and the test code size. The method consists of four parametric phases and can deal with different VLIW processor models. The main goal of the paper is to show that in the case of VLIW processors it is possible to automatically generate an effective test program able to achieve high fault coverage with minimal test time and required resources. Experimental data gathered on a case study demonstrate the effectiveness of the proposed approach: results show that this method is able to exploit the intrinsic parallelism of the VLIW processor, taming the growth in size andduration of the test program when the processor size grows.