This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC'99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques.
An efficient fault simulation technique for transition faults in non-scan sequential circuits / Bosio, A; Girard, P; Pravossoudovich, S; Bernardi, Paolo; SONZA REORDA, Matteo. - (2009), pp. 50-55. (Intervento presentato al convegno 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 tenutosi a Liberec (Czech Republic) nel April 15-17, 2009) [10.1109/DDECS.2009.5012098].
An efficient fault simulation technique for transition faults in non-scan sequential circuits
BERNARDI, PAOLO;SONZA REORDA, Matteo
2009
Abstract
This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC'99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques.Pubblicazioni consigliate
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https://hdl.handle.net/11583/2261134
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