This paper proposes a new approach for designing a cost-effective, on-chip, hardware pattern generator of deterministic test sequences. Given a pre-computed test pattern (obtained by an ATPG tool) with predetermined fault coverage, a hardware Test Pattern Generator (TPG) based on Autonomous Finite State Machines (AFSM) structure is synthesized to generate it. This new approach exploits “don’t care” bits of the deterministic test patterns to lower area overhead of the TPG. Simulations using benchmark circuits show that the hardware components cost is considerably less when compared with alternative solutions.

AFSM-based deterministic hardware TPG / Benso, Alfredo; DI CARLO, Stefano; DI NATALE, Giorgio; Prinetto, Paolo Ernesto. - STAMPA. - (2005), pp. 178-181. ((Intervento presentato al convegno IEEE 8th Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) tenutosi a Sopron, HU nel 13-16 Apr. 2005.

AFSM-based deterministic hardware TPG

BENSO, Alfredo;DI CARLO, STEFANO;DI NATALE, Giorgio;PRINETTO, Paolo Ernesto
2005

Abstract

This paper proposes a new approach for designing a cost-effective, on-chip, hardware pattern generator of deterministic test sequences. Given a pre-computed test pattern (obtained by an ATPG tool) with predetermined fault coverage, a hardware Test Pattern Generator (TPG) based on Autonomous Finite State Machines (AFSM) structure is synthesized to generate it. This new approach exploits “don’t care” bits of the deterministic test patterns to lower area overhead of the TPG. Simulations using benchmark circuits show that the hardware components cost is considerably less when compared with alternative solutions.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11583/1499954
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