An optimizing C front-end for hardware synthesis

Modern embedded systems must execute a variety of high performance real-time tasks, such as audio and image compression and decompression, channel coding and encoding, etc. High hardware design and mask production costs dictate the need to re-use an architectural platform for as many applications as possible. Reconfigurable platforms can be very effective in these cases, because they allow one to re-use the architecture across a variety of applications. The efficient use of a reconfigurable platform requires a methodology and tools supporting it in order to extensively explore the hardware/software design space, without requiring developers to have a deep knowledge of the underlying architecture, since they often have a software background and only limited hardware design skills. This paper describes a tool that fits into a complete design flow for a reconfigurable processor and that allows one to efficiently transform a high level specification into a lower level one, more suitable for synthesis on the reconfigurable array. The effectiveness of the methodology is proved by a complete implementation of a turbo-decoder.