Archivio Istituzionale della RicercaCONDO, CARLO
CONDO, CARLO
Dipartimento di Elettronica e Telecomunicazioni
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Risultati 1 - 6 di 6 (tempo di esecuzione: 0.019 secondi).
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications
2014 Condo, Carlo; Martina, Maurizio; RUO ROCH, Massimo; Masera, Guido
A joint communication and application simulator for NoC-based custom SoCs: LDPC and turbo codes parallel decoding case study
2013 Condo, Carlo; Baghdadi, Amer; Masera, Guido
Concatenated Turbo/LDPC codes for deep space communications: performance and implementation
2013 Condo, Carlo
FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories
2013 Syed, Zaidi; M., Awais; Condo, Carlo; Martina, Maurizio; Masera, Guido
A Network-on-Chip-based turbo/LDPC decoder architecture
2012 Condo, Carlo; Martina, Maurizio; Masera, Guido
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods
2011 Condo, Carlo; Masera, Guido
| Citazione | Data di pubblicazione | Autori | File |
|---|---|---|---|
| Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-based applications / Condo, C., Martina, M., RUO ROCH, M., Masera, G.. - ELETTRONICO. - 1:(2014), pp. 418-423. (Euromicro International Conference on Parallel, Distributed and Network-Based Processing Torino febbraio 2014) [10.1109/PDP.2014.85]. | 1-gen-2014 | CONDO, CARLOMARTINA, MAURIZIORUO ROCH, MassimoMASERA, Guido | bare_conf.pdf |
| A joint communication and application simulator for NoC-based custom SoCs: LDPC and turbo codes parallel decoding case study / Condo, C., Baghdadi, A., Masera, G.. - STAMPA. - (2013), pp. 168-174. (Digital System Design, 2013 Euromicro Conference on Santander 4-6 Settembre 2013) [10.1109/DSD.2013.26]. | 1-gen-2013 | CONDO, CARLOBAGHDADI, AMERMASERA, Guido | - |
| Concatenated Turbo/LDPC codes for deep space communications: performance and implementation / Condo, C.. - ELETTRONICO. - (2013), pp. 1-6. (SPACOMM 2013 Mestre 21-26 Aprile 2013). | 1-gen-2013 | CONDO, CARLO | LDPCturboConcat.pdf |
| FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories / Syed, Z., M., A., Condo, C., Martina, M., Masera, G.. - STAMPA. - (2013), pp. 190-195. (Design and Architectures for Signal and Image Processing (DASIP) Cagliari, Italy 8-10 Oct. 2013). | 1-gen-2013 | CONDO, CARLOMARTINA, MAURIZIOMASERA, Guido + | - |
| A Network-on-Chip-based turbo/LDPC decoder architecture / Condo, C., Martina, M., Masera, G.. - STAMPA. - (2012), pp. 1525-1530. (Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012 Dresden (D) 12-16 Mar. 2012) [10.1109/DATE.2012.6176715]. | 1-gen-2012 | CONDO, CARLOMARTINA, MAURIZIOMASERA, Guido | DATE 2012.pdf |
| A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods / Condo, C., Masera, G.. - STAMPA. - (2011), pp. 1-8. (2011 Conference on Design and Architectures for Signal and Image Processing (DASIP) Tampere (FIN) 2-4 Nov. 2011) [10.1109/DASIP.2011.6136889]. | 1-gen-2011 | CONDO, CARLOMASERA, Guido | DASIP_2011.pdf |