Reproducible Builds as a Security Property for Open FPGA-Based Hardware Security Modules Design

Hardware Security Modules (HSMs), secure elements, and Root of Trusts (RoTs) protect cryptographic operations and secrets, but their hardware artifacts and implementation flows are often difficult to verify independently. This paper argues that reproducibility should be treated as a security property for code-defined hardware, firmware, and software artifacts, and evaluates this claim in the Field-Programmable Gate Array (FPGA) setting. We present a minimal FPGA-based HSM building block composed of a RISC-V processor, a coherent-sampling oscillator True Random Number Generator (TRNG), and a hardware Secure Hash Algorithm (SHA)-256 module. The design is instantiated with VexRiscv and Ibex to assess portability across open RISC-V control cores. A Nix flake pins the hardware-generation, verification, synthesis-input, and firmware dependencies, enabling auditors to rebuild the generated Register-Transfer Level (RTL), reproduce the OpenTRNG verification workflow, execute firmware-level tests, and validate the SHA-256 module through known-answer tests. The result is a reproducible and auditable FPGA-based security substrate whose guarantees hold up to the explicit synthesis boundary, where proprietary vendor tooling remains a residual trust assumption.