Development of a 7-nm SET-Hardened Reconfigurable Logic Array

This paper presents a 7-nm SET-hardened reconfigurable logic array implemented using the ASAP7 FinFET technology. The work aims to establish a practical foundation for the development of radiation-hardened FPGAs at advanced technology nodes. The proposed array comprises 200 single event transient (SET)-hardened basic logic elements (BLEs), each integrating a 6-input look-up-table (LUT), a D flip-flop (DFF), and an output-selection multiplexer (MUX). Each component is analyzed through fault injection and selectively hardened against SET-induced failures. The resulting BLE achieves a substantial reduction in estimated SET cross section while introducing only moderate area, timing, and power overheads. The complete array is physically implemented using the OpenROAD flow, and a dedicated RTL-to-array mapping tool is developed to translate Verilog descriptions into BLE assignments, LUT configurations, and transistor-level interconnections. A comprehensive case study further demonstrates that the proposed logic array can implement practical circuits with improved SET resilience and limited additional overhead.