Development of a Radiation-Hardened Standard Cell Library in 7 nm FinFET Technology

As technology scales to advanced FinFET nodes, digital circuits become increasingly susceptible to radiation induced soft errors, creating a major reliability concern for safety-critical and space applications. Conventional hardening often requires extensive circuit-level vulnerability analysis, leading to substantial design time and effort. This paper presents a radiation-hardened (RH) standard cell library for 7 nm FinFET technology based on the ASAP7 PDK, aiming to improve radiation resilience while limiting both overhead and design time. The library is developed through transistor level fault injection and 3D layout-aware particle-strike simulation to derive customized hardening strategies for individual cells. Experimental results show that the RH cells achieve significantly higher threshold LET and shorter error duration than standard counterparts. Case studies on a D flip-flop and a C432 benchmark further demonstrate significantly reduced SEE cross-section with modest area, power, and delay over heads, confirming a practical and scalable approach to SEE resilient design in advanced FinFET circuits.