Optimizing Scan Test Economics Trade-Offs in Homogeneous 3D SICs via Cost Modeling

This paper presents a scan test cost optimization model tailored for 3D stacked integrated circuits (3D SICs), designed to reduce test cost by decreasing Wafer Sort test time. The transition from traditional planar manufacturing to vertical integration introduces cost losses when test escapes are detected late in the assembly process, leading to the loss of Known Good Dies (KGDs) stacked in defective units. To address this, a scan test cost model is proposed that integrates yield, Wafer Sort, progressive partial assembly tests, and final Package Test costs. The proposed model uses a recursive cost formulation and known weighted fault metrics to evaluate if the test time saved exclusively at the Wafer Sort level justifies the extra cost of scrapped KGD and 3D packages. The proposed model is validated using six months of high volume manufacturing data from a 20 million gate industrial automotive SoC. Although the source data comes from a planar 2D process, a simulated stacking methodology is used to mathematically evaluate virtual 4-layer and 8-layer 3D configurations. Experimental results show that progressive intermediate testing successfully mitigates the KGD scrap cost, yielding maximum economic gains of up to 3.44% for 8-layer stacks. Furthermore, coupling the framework with criticality-oriented pattern set nearly doubles these benefits, achieving overall cost reductions of 6%.