Performance-aware reliability optimization for digital designs

Nanoscale technologies are reaching high performance data centers. With the scaling of transistor sizes down to 2nm the susceptibility of designs to Single Event Upsets (SEUs) is ever-increasing. To provide Reliability, and avoid phenomena like Silent Data Corruption (SDC), hardening strategies need to be implemented during the implementation process. Reaching meaningful levels of compliance can significantly impact the Performance, Power and Area (PPA) of the final design. High-performance data centers require designs to operate at very high clock speeds but hardened designs often come with degraded performance. This paper presents a novel methodology to tackle the performance degradation problem from different angles. A new classification metric, called Criticality, is proposed to provide a novel methodology for the prioritization of registers to be hardened. Additionally, a Criticality-based dynamic decision tree is proposed and discussed. Finally, an automated flow for performing an optimized hardening is provided. The Safety Specification Format (SSF) is used as an exchange format between the different steps of the flow. An assessment of the results is given for the CV32E40P and CVA6 open-source RISC-V processors. Validation results are demonstrated and shown through trend comparison with respect to traditional hardening methodologies.