FSWGEN: a Device-tree Specification driven System-Level Test workload generator

This paper explores the portability and reusability of functional System-Level Test (SLT) methodologies across different System-on-Chip (SoC) design architectures. The proposed approach leverages the Device-tree Specification (DTS) of the Device-Under-Test (DUT) to enable automated test generation. By constructing a graph representation from the DTS, the methodology facilitates the creation of functional test programs across different SoC architectures through a simple graph traversal process, making it highly adaptable and efficient in simplifying SLT development.