About the correlation between logical identified faulty gates and their layout characteristics

Electronics play a significant role in modern society in various areas of our daily lives. Companies producing embedded nano-electronic systems have responded to the ever-increasing demand for high-performance chips with the development and production of structurally complex design, both in terms of the number of gates they are composed of and how they are arranged on the silicon surface. Especially devices intended for safety-critical fields, such as the Automotive field, require a thorough and precise testing process before they are fielded. This paper proposes a correlation analysis between candidate faulty logical gates as possible sources of a given failure identified during the Manufacturing Test Flow and their layout characteristics on the silicon. It is meaningful feedback for manufacturers about the quality of their applied tests. The experimental results are reported for data regarding a production lot of an Automotive System-on-Chip belonging to the SPC58 family produced by STMicroelectronics.