PORTO @ 
Archivio Istituzionale della Ricerca
IRIS è la soluzione IT che facilita la raccolta e la gestione dei dati relativi alle attività e ai prodotti della ricerca. Fornisce a ricercatori, amministratori e valutatori gli strumenti per monitorare i risultati della ricerca, aumentarne la visibilità e allocare in modo efficace le risorse disponibili.
EnglishThis paper presents a fully differential 12-bit SAR ADC developed for high-voltage CMOS sensors. The converter has been designed in compliance with low power consumption, high resolution and low material budget requirements. A merged capacitor switching method is employed to decrease power consumption and the capacitor array has been split up into two sub-DACs in order to reduce the area. The prototype has been implemented in a 110-nm CMOS technology. With a power supply of 1.2 V and a 100 MHz clock, simulations show an ENOB 9.87 of and a SFDR of 73.42 dB. The power consumption of the ADC is 513 uW while the Figure of Merit (FOM) results 54.8 fJ/conv-step. The final chip includes also a calibration engine to minimize the capacitor mismatch effect thus further improving the resolution.
A 12-bit 100 MHz SAR ADC in 110-nm CMOS for MAPSs / Tedesco, Silvia. - ELETTRONICO. - (2021), pp. 252-255. ((Intervento presentato al convegno SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME tenutosi a online nel 19-22 Luglio 2021.
| Titolo: | A 12-bit 100 MHz SAR ADC in 110-nm CMOS for MAPSs | |
| Autori: | ||
| Data di pubblicazione: | 2021 | |
| Abstract: | This paper presents a fully differential 12-bit SAR ADC developed for high-voltage CMOS sensors. ...The converter has been designed in compliance with low power consumption, high resolution and low material budget requirements. A merged capacitor switching method is employed to decrease power consumption and the capacitor array has been split up into two sub-DACs in order to reduce the area. The prototype has been implemented in a 110-nm CMOS technology. With a power supply of 1.2 V and a 100 MHz clock, simulations show an ENOB 9.87 of and a SFDR of 73.42 dB. The power consumption of the ADC is 513 uW while the Figure of Merit (FOM) results 54.8 fJ/conv-step. The final chip includes also a calibration engine to minimize the capacitor mismatch effect thus further improving the resolution. | |
| ISBN: | 978-3-8007-5588-2 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| Tedesco Silvia - A 12-bit 100 MHz SAR ADC in 110-nm CMOS for MAPSs- PRIME 2021.pdf | Articolo principale | 2. Post-print / Author's Accepted Manuscript | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri |
| A_12-bit_100_MHz_SAR_ADC_in_110-nm_CMOS_for_MAPSs.pdf | Articolo principale | 2. Post-print / Author's Accepted Manuscript | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2929016
Copyright © 2022