In integrated circuit designs, the conductive connections between different layers are known as vias or cuts. Such structures are critical for digital circuit manufacturing, as they represent a common defect location. A well-established DfM/DfR rule suggests replicating every via instance for increasing dependability by means of redundancy. When this is not achievable, such as when area and routing layers are limited, and when the circuit is particularly congested, a mandatory requirement is that the remaining single vias must be tested. We propose an automated method for accurately evaluating test coverage of faults related to defective vias, ready for use in any digital implementation flow and for integration within EDA tools, and also providing a useful quality metric. This article extends a previously published paper on this topic [2], with the introduction of a practical approach relying on both scan-based and functional testing to meet quality requirements in terms of single via defect coverage: functional stimuli complement the automatically-generated scan pattern set to reach the desired target at a limited cost. A prototype tool implementation for single via defect coverage computation is described, and experimental results for two industrial case studies are reported.

Testing single via related defectsin digital VLSI designs / Mirabella, Nunzio; Ricci, Maurizio; Calà, Ignazio; Lanza, Roberto; Grosso, Michelangelo. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - ELETTRONICO. - 120 (114100):(2021). [10.1016/j.microrel.2021.114100]

Testing single via related defectsin digital VLSI designs

Mirabella, Nunzio;Grosso, Michelangelo
2021

Abstract

In integrated circuit designs, the conductive connections between different layers are known as vias or cuts. Such structures are critical for digital circuit manufacturing, as they represent a common defect location. A well-established DfM/DfR rule suggests replicating every via instance for increasing dependability by means of redundancy. When this is not achievable, such as when area and routing layers are limited, and when the circuit is particularly congested, a mandatory requirement is that the remaining single vias must be tested. We propose an automated method for accurately evaluating test coverage of faults related to defective vias, ready for use in any digital implementation flow and for integration within EDA tools, and also providing a useful quality metric. This article extends a previously published paper on this topic [2], with the introduction of a practical approach relying on both scan-based and functional testing to meet quality requirements in terms of single via defect coverage: functional stimuli complement the automatically-generated scan pattern set to reach the desired target at a limited cost. A prototype tool implementation for single via defect coverage computation is described, and experimental results for two industrial case studies are reported.
File in questo prodotto:
File Dimensione Formato  
singlevia_microrel_v04.pdf

Open Access dal 31/03/2023

Descrizione: Accepted Paper MR - Authors' postprint
Tipologia: 2. Post-print / Author's Accepted Manuscript
Licenza: Creative commons
Dimensione 629.32 kB
Formato Adobe PDF
629.32 kB Adobe PDF Visualizza/Apri
1-s2.0-S0026271421000664-main (1).pdf

non disponibili

Descrizione: Accepted Paper MR - Editorial Version
Tipologia: 2a Post-print versione editoriale / Version of Record
Licenza: Non Pubblico - Accesso privato/ristretto
Dimensione 2.12 MB
Formato Adobe PDF
2.12 MB Adobe PDF   Visualizza/Apri   Richiedi una copia
Pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2920412