Testing single via related defectsin digital VLSI designs

In integrated circuit designs, the conductive connections between different layers are known as vias or cuts. Such structures are critical for digital circuit manufacturing, as they represent a common defect location. A well-established DfM/DfR rule suggests replicating every via instance for increasing dependability by means of redundancy. When this is not achievable, such as when area and routing layers are limited, and when the circuit is particularly congested, a mandatory requirement is that the remaining single vias must be tested. We propose an automated method for accurately evaluating test coverage of faults related to defective vias, ready for use in any digital implementation flow and for integration within EDA tools, and also providing a useful quality metric. This article extends a previously published paper on this topic [2], with the introduction of a practical approach relying on both scan-based and functional testing to meet quality requirements in terms of single via defect coverage: functional stimuli complement the automatically-generated scan pattern set to reach the desired target at a limited cost. A prototype tool implementation for single via defect coverage computation is described, and experimental results for two industrial case studies are reported.