With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
An intra-cell defect grading tool / Bosio, A.; Dilillo, L.; Girard, P.; Todri-Sanial, A.; Virazel, A.; Bernabovi, S.; Bernardi, P.. - (2014), pp. 298-301. (Intervento presentato al convegno 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014 tenutosi a pol nel 2014) [10.1109/DDECS.2014.6868814].
An intra-cell defect grading tool
Bernabovi S.;Bernardi P.
2014
Abstract
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.File | Dimensione | Formato | |
---|---|---|---|
06868814.pdf
accesso riservato
Tipologia:
2a Post-print versione editoriale / Version of Record
Licenza:
Non Pubblico - Accesso privato/ristretto
Dimensione
264.13 kB
Formato
Adobe PDF
|
264.13 kB | Adobe PDF | Visualizza/Apri Richiedi una copia |
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
https://hdl.handle.net/11583/2909180