With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.

An intra-cell defect grading tool / Bosio, A.; Dilillo, L.; Girard, P.; Todri-Sanial, A.; Virazel, A.; Bernabovi, S.; Bernardi, P.. - (2014), pp. 298-301. (Intervento presentato al convegno 17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014 tenutosi a pol nel 2014) [10.1109/DDECS.2014.6868814].

An intra-cell defect grading tool

Bernabovi S.;Bernardi P.
2014

Abstract

With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
2014
978-1-4799-4558-0
978-1-4799-4560-3
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11583/2909180