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EnglishIn-field Self-Test of safety-critical devices becomes very important due to the stringent requirements introduced by the current standards such as IEC 61805 and ISO 26262. These standards aim at guaranteeing that electronic systems are working correctly in safety-critical application such as automotive field. Several solutions have been provided, encompassing Software with Software-Based Self-Test (SBST) and Hardware approaches with Build-In Self-Test (BIST). In this paper, we proposed a novel scheme enabling the chip to be very fast and accurately tested by the concurrent execution of SBST and Logic BIST procedures. The paper describes how to design and use a Design-for-Testability (DfT) infrastructure to enable such a concurrent executions of different test strategies. Experimental results are demonstrating the feasibility of the approach and underline the obtained benefit on significant computational modules of the Open-RISC 1200 architecture.
A hybrid in-field self-test technique for SoCs / Carbonara, S.; Bernardi, P.; Restifo, M.. - (2019), pp. 1-6. ((Intervento presentato al convegno 14th IEEE International Conference on Design and Technology of Integrated Systems In Nanoscale Era, DTIS 2019 tenutosi a grc nel 2019 [10.1109/DTIS.2019.8735075].
| Titolo: | A hybrid in-field self-test technique for SoCs | |
| Autori: | ||
| Data di pubblicazione: | 2019 | |
| Abstract: | In-field Self-Test of safety-critical devices becomes very important due to the stringent require...ments introduced by the current standards such as IEC 61805 and ISO 26262. These standards aim at guaranteeing that electronic systems are working correctly in safety-critical application such as automotive field. Several solutions have been provided, encompassing Software with Software-Based Self-Test (SBST) and Hardware approaches with Build-In Self-Test (BIST). In this paper, we proposed a novel scheme enabling the chip to be very fast and accurately tested by the concurrent execution of SBST and Logic BIST procedures. The paper describes how to design and use a Design-for-Testability (DfT) infrastructure to enable such a concurrent executions of different test strategies. Experimental results are demonstrating the feasibility of the approach and underline the obtained benefit on significant computational modules of the Open-RISC 1200 architecture. | |
| ISBN: | 978-1-7281-3424-6 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
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| File | Descrizione | Tipologia | Licenza | |
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http://hdl.handle.net/11583/2909174
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