A hybrid in-field self-test technique for SoCs

In-field Self-Test of safety-critical devices becomes very important due to the stringent requirements introduced by the current standards such as IEC 61805 and ISO 26262. These standards aim at guaranteeing that electronic systems are working correctly in safety-critical application such as automotive field. Several solutions have been provided, encompassing Software with Software-Based Self-Test (SBST) and Hardware approaches with Build-In Self-Test (BIST). In this paper, we proposed a novel scheme enabling the chip to be very fast and accurately tested by the concurrent execution of SBST and Logic BIST procedures. The paper describes how to design and use a Design-for-Testability (DfT) infrastructure to enable such a concurrent executions of different test strategies. Experimental results are demonstrating the feasibility of the approach and underline the obtained benefit on significant computational modules of the Open-RISC 1200 architecture.