In a recent paper, a through-the-barrier communication technique suitable for isolated resonant converters has been proposed. The approach is capable of sending data bidirectionally at high speed (one bit for each converter clock period) without the need of any additional isolating device other than the transformer necessary for the power transfer, and has been demonstrated by means of a proof-of-concept low-frequency prototype. In this paper we review that work under the assumption of increasing the operating frequency by using a coreless transformer presenting low losses, but also a low coupling factor k. This allows to increase the efficiency of the converter to a very high value (92% in the proposed design working at 6.78 MHz), but the communication speed has to be reduced (one bit every four clock cycles).
Through-The-Barrier Communications in Isolated Class-E Converters Embedding a Low-k Transformer / Pareschi, Fabio; Celentano, Andrea; Mangia, Mauro; Rovatti, Riccardo; Setti, Gianluca. - STAMPA. - (2020), pp. 1-5. (Intervento presentato al convegno 2020 IEEE International Symposium on Circuits and Systems nel October 10-21, 2020) [10.1109/ISCAS45731.2020.9180486].
Through-The-Barrier Communications in Isolated Class-E Converters Embedding a Low-k Transformer
Pareschi, Fabio;Celentano, Andrea;Setti, Gianluca
2020
Abstract
In a recent paper, a through-the-barrier communication technique suitable for isolated resonant converters has been proposed. The approach is capable of sending data bidirectionally at high speed (one bit for each converter clock period) without the need of any additional isolating device other than the transformer necessary for the power transfer, and has been demonstrated by means of a proof-of-concept low-frequency prototype. In this paper we review that work under the assumption of increasing the operating frequency by using a coreless transformer presenting low losses, but also a low coupling factor k. This allows to increase the efficiency of the converter to a very high value (92% in the proposed design working at 6.78 MHz), but the communication speed has to be reduced (one bit every four clock cycles).File | Dimensione | Formato | |
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https://hdl.handle.net/11583/2867036