A JTAG-based Fault Emulation Platform for Dependability Analyses of Processor-based ASICs

This paper presents a fault emulation platform to support dependability analyses of safety-critical ASICs. Differently than existing works, the focus of this paper is the fault detection mechanism that allows to mimic the detection mechanisms of a fault simulator (including fault dropping). The proposed platform can be integrated in the already-existing JTAG infrastructure of the target ASIC. Therefore, it can be easily accessed with standard tools and perfectly compatible with the modern industrial FPGA-based emulators.