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EnglishThis work contains the structure and transistor-level design of CMOS single-ended to differential-ended converter for the front-end integrated circuit. The front-end is used to readout large area SiPM at LAr temperature (87 K). The converter circuit, a fully-differential amplifier and two non-inverter amplifiers, was implemented using a standard 110 nm CMOS technology. Fully differential stage was designed using a Folded Cascode Operational Trans-impedance Amplifier (OTA) with a common mode feedback, a power rail of +1.25 V and -1.25 V, a power consumption of 20 mW and an unity gain in closed-loop. The converter circuit is connected, on the input, to a front-end integrated circuit. The front-end readout a SiPM tile of 24 cm2 produced in the Darkside collaboration project. The circuit converts a single-ended signal, with a peaking time of 250 ns, a timing jitter of 10 ns and SNR larger than 10, into a differential output.
Single-ended to differential output converter for a 4-Channel front-end integrated circuit in liquid argon / Martinez Rojas, Alejandro David. - 2019-(2019), pp. 231-234. ((Intervento presentato al convegno 31st International Conference on Microelectronics, ICM 2019 tenutosi a egy nel 2019 [10.1109/ICM48031.2019.9021772].
| Titolo: | Single-ended to differential output converter for a 4-Channel front-end integrated circuit in liquid argon | |
| Autori: | ||
| Data di pubblicazione: | 2019 | |
| Abstract: | This work contains the structure and transistor-level design of CMOS single-ended to differential...-ended converter for the front-end integrated circuit. The front-end is used to readout large area SiPM at LAr temperature (87 K). The converter circuit, a fully-differential amplifier and two non-inverter amplifiers, was implemented using a standard 110 nm CMOS technology. Fully differential stage was designed using a Folded Cascode Operational Trans-impedance Amplifier (OTA) with a common mode feedback, a power rail of +1.25 V and -1.25 V, a power consumption of 20 mW and an unity gain in closed-loop. The converter circuit is connected, on the input, to a front-end integrated circuit. The front-end readout a SiPM tile of 24 cm2 produced in the Darkside collaboration project. The circuit converts a single-ended signal, with a peaking time of 250 ns, a timing jitter of 10 ns and SNR larger than 10, into a differential output. | |
| ISBN: | 978-1-7281-4058-2 | |
| Appare nelle tipologie: | 4.1 Contributo in Atti di convegno |
File in questo prodotto:
| File | Descrizione | Tipologia | Licenza | |
|---|---|---|---|---|
| Egypt_conference-2.pdf | 2. Post-print / Author's Accepted Manuscript | PUBBLICO - Tutti i diritti riservati | Visibile a tuttiVisualizza/Apri | |
| Martinez-Rojas-Single-ended.pdf | 2a Post-print versione editoriale / Version of Record | Non Pubblico - Accesso privato/ristretto | Administrator Richiedi una copia |
http://hdl.handle.net/11583/2837860
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